The present invention is directed to communications systems, and more particularly to a system and method for controlling the difference between charge-up and charge-down currents in a charge pump circuit.
In modem communications systems, bidirectional data is transmitted in digital format. Transmission of data in digital, as opposed to analog, form has numerous advantages, mainly the ability to recreate the data at the receiver. Analog transmissions are affected by various problems, as is well documented in the art. However, digital transmissions are easily reconstituted at the receiver, provided the receiver is able to regenerate the transmission with the fewest number of bit errors. This requires the receiver to sample the transmission at an optimal rate and at an optimum time. To conserve bandwidth, digital data transmissions typically combine the data itself with a clock signal. In order to retrieve the clock signal from the transmission, a phase locked loop is used for clock signal recovery.
A phase locked loop is an electronic circuit with a voltage or current controlled oscillator that is constantly adjusted to match, in phase, the frequency of an input signal. In addition to stabilizing a particular communications channel, a phase locked loop may be used to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency. In other words, phase locked loops compare the frequency and/or phase of an incoming datastream to a periodic reference clock signal generated by an oscillator circuit, and to adjust the oscillator circuit until its output matches, in both frequency and phase, the data signal. This generates a reference clock which controls operation of the remainder of the circuit, thereby allowing for the regeneration of the incoming data signal. Typical phase locked loop circuits are manufactured as integrated circuits.
The phase locked loop normally consists of a phase detector, a charge pump circuit, a loop filter and a voltage controlled oscillator. The phase detector is a device that compares two input frequencies, generating an output that is a measure of their phase difference. For example, if the two input signals differ in frequency, the phase detector gives a periodic output at the difference frequency. Thus, upon receiving a data signal at a data input of the phase detector, the detector compares, in time, the data signal's rising edge with the rising edge of an output signal of the voltage controlled oscillator.
For example, if the phase detector determines that the input signal leads the voltage controlled oscillator signal, it will direct the charge pump to increase the current into the voltage controlled oscillator, thereby increasing the voltage controlled oscillator signal. In the event that the datastream lags the voltage controlled oscillator signal, the phase detector will direct the charge pump to decrease the amount of current flowing into the voltage controlled oscillator. In essence, the charge pump sources or sinks a particular amount of current to or from the loop filter. The voltage is thus used to control the operational frequency of the voltage controlled oscillator. The operational frequency of the voltage controlled oscillator is thus increased or decreased to reduce phase lead or phase lag of the inputs to the phase detector.
Referring now to FIG. 1, there is shown a simplified illustration of a phase locked loop circuit 100 comprising a charge pump 140. Charge pump 140 comprises transistors 102, 104, 106 and 108. Transistors 102 and 108 are used to generate a constant current. A first voltage 132 is applied to the gate of transistor 102 and a second voltage 134 is applied to gate of transistor 108 which control the amount of current supplied by transistors 102 and 108 respectively. Transistors 104 and 106 operate as switches, acting as switches for connecting transistors 102 and 108 respectively to the output terminal 130 of the charge pump which is connected to the input terminal VCNT 112 of voltage controlled oscillator VCO 110. As shown in FIG. 1, the voltage at output terminal 130 will take various voltages, depending upon the operating frequency of VCO 110. UP switches transistor 104 on when the voltage at output terminal 130 needs to be increased, while DOWN switches transistor 106 on to decrease the voltage at output terminal 130. A phase locked loop filter 114 is operatively coupled between output terminal 130 of to the VCNT terminal 112 is a phase locked loop filter 114. The phase locked loop filter 114 comprises capacitance 116, resistance 118 and capacitance 120. It will be appreciated by those skilled in the art that the corresponding values of the resistance and capacitance will be readily ascertainable during the building of the circuit.
The voltage at VCNT 112 of VCO 110 depends on the frequency generated by VCO 110. This can cause a variance in the current generated by either transistor 102 and transistor 108. This is because a real transistor's characteristic curve is not perfect. A real transistor's current has some dependency on the voltage between its drain and source. The absolute value of the current source affects the filter characteristic of the phased locked loop and the difference between the pull-up current and the pull-down current result in a phase offset of the phase locked loop. For example, if VCNT is decreasing, as it approaches ground voltage, the current from transistor 108 becomes weak, which creates a corresponding phase offset in phase locked loop 100. Similarly, if VCNT increased and approaches VDD, the current from transistor 102 becomes weak and will create a phase offset in phase locked loop 100.